This application relates generally to electronic circuitry, and more particularly to pulse width modulation methodology and circuitry.
FIG. 1A shows an example of a count plot 100, having an amplitude proportional to count, and representative of a pulse width modulation (PWM) control counter 102 against time, and an example of a timing diagram 104 of a PWM waveform 106 generated using the control counter 102. (Herein, “control count” refers to both a count generator, and a resulting count. The count of the control counter is referred to when appropriate for clarification.) The count plot 100 and the timing diagram 104 use the same time axis. Accordingly, a count value in the control counter 102 expressed at a particular point on the x-axis (time axis) in the count plot 100 and a PWM value (high or low) in the PWM waveform 106 expressed at the same point on the x-axis (time axis) in the timing diagram 104 are being expressed at the same time. This time axis alignment applies to each of the figures herein which include a plot of a PWM control counter and a timing diagram of a PWM waveform generated using the control counter.
The example PWM control counter 102 and PWM waveform 106 shown in FIG. 1A correspond to typical PWM control. The control counter 102 counts from a minimum value, generally zero, up to a maximum value (incrementing), and then restarts the count from the minimum value. This results in a sawtooth pattern. The control counter 102 is compared against two thresholds, a rising edge threshold 108 and a falling edge threshold 110, to cause rising and falling edges (respectively) in the PWM waveform 106. The rising edge threshold 108 corresponds to the maximum count of the control counter 102, which corresponds to a desired frequency of the PWM waveform 106. The falling edge threshold 110 corresponds to one half (½) of the maximum count of the control counter 102, corresponding to a 50% duty cycle in the PWM waveform 106. The falling edge threshold 110 fraction of the maximum count can be adjusted to adjust the duty cycle of the PWM waveform 106.
A first desired frequency F1, designated for a time T0 to a time T1, corresponds to a maximum count of C=1000 counts. A second desired frequency F2, designated for a time T1 to a time T2, corresponds to a maximum count of C=400 counts. A third desired frequency F3, designated for a time T2 to a time T3, corresponds to a maximum count of C=1000 (F1=F3). The rising edge threshold 108 of F1 and F3 is 1000 counts, and the falling edge threshold 110 of F1 and F3 is 500 counts. The rising edge threshold 108 of F2 is 400, and the falling edge threshold 110 of F2 is 200. Times T0, T1, T2, and T3 are the same times in FIGS. 1A, 1B and 1C.
The minimum count of the control counter 102 is C=0 counts. If the minimum count were higher, such as C=50 counts, then the respective frequencies would be higher because of the smaller differences between maximum and minimum counts. The frequencies would be the same if the minimum counter were higher, such as C=50 counts, and the maximum counts were equally increased, accordingly, to F1=F3=1050 counts, and F2=450 counts. That is, the frequency (and period) of the control counter 102 depends on the difference between the maximum and minimum counts of a period of the control counter 102.
FIG. 1B shows a prior art example of a count plot 112 of a PWM control counter 114 against time, and an example of a timing diagram 116 of a PWM waveform 118 generated using the control counter 114. The count plot 112 and the timing diagram 116 use the same time axis. The control counter 102 of FIG. 1A acts as a master control counter with respect to the control counter 114 of FIG. 1B. This means that the control counter 114 values for the count (except during a period which spans or is next subsequent to a change in frequency or phase delay), frequencies (maximum and minimum count values), and thresholds of FIG. 1B are the same as the control counter 102 values for the count, frequencies, and thresholds of FIG. 1A; except that the (slave) control counter 114 of FIG. 1B is phase shifted +180° with respect to the (master) control counter 102 of FIG. 1A.
As used herein, “phase shift” refers to an angle of rotation (a fractional shift) of a period of a slave control counter with respect to a period of a master control counter. As used herein, “phase delay count” refers to a count value by which, for a corresponding phase shift applied to and a current frequency of the slave control counter, the period of the slave control counter is shifted with respect to the period of the master control counter. The phase delay count corresponds to a number of increments of the master control counter, after the master control counter reaches a particular value while incrementing or decrementing, before the slave control counter reaches the particular value while incrementing or decrementing, respectively. In FIG. 1B, between times T0 and T1, and between times T2 and T3, the phase delay count of the control counter 114 with respect to the master control counter 102 is 50% of 1000, that is, 0.5*1000=500 counts (+180° corresponds to a delay of 50% of a single period). Between times T1 and T2, the phase delay count of the control counter 114 with respect to the master control counter 102 is 400*0.5=200 counts.
When the control counter 114 transitions from F1 to F2 at time T1, the count of the control counter 114 is phase shifted +180° with respect to the count at time T1 of the control counter 102 of FIG. 1A. To maintain the +180° phase shift and the new frequency, the count at time T1 changes from a count corresponding to the previous frequency (C=499 counts) to a count corresponding to the new frequency (C=200 counts). (A similar change from C=199 to C=500 counts occurs at the control counter 114 transition from F2 to F3 at time T2.) As a result, the continuing incrementing of the control counter 114 is interrupted and, consequently, the falling edge threshold 120 is not reached at time T1 on transition from F1 to F2, because the control counter 114 count jumps to (does not properly increment to) 200 at time T1, and thresholds do not change until the end of a period. Accordingly, in FIG. 1B and at time T1, when the control counter 114 would increment to and reach the falling edge threshold 120 if there were no frequency change, the control counter 114 jumps to—does not increment to—the falling edge threshold 120. Therefore, no falling edge is triggered in the PWM waveform 118 at time T1, as shown by the dotted vertical line beginning a missed cycle 128 in FIG. 1B at time T1. Similarly, at time T2, when the incrementing control counter 114 would reach a falling edge threshold 120 if there were no frequency change, the control counter 114 does not increment to the falling edge threshold 120, and no falling edge is triggered in the PWM waveform 118 at time T2, as shown by another dotted vertical line beginning a missed cycle 128 in FIG. 1B at time T2. (There is also a rising edge threshold 122.)
Changes in frequency in a PWM control counter can cause discontinuities 124 in the count maintained by the PWM control counter. Such discontinuities 124 can, in turn, cause errors in a PWM waveform controlled by the PWM control counter. In FIG. 1B, dotted lines in the PWM waveform 118 show intended portions 128 of the PWM waveform 118, and deviations from this intention—shown using dashed lines—include erroneous portions 126 of the PWM waveform 118. PWM waveform 118 errors can cause extended periods in the PWM waveform 118 at frequency transitions. Extended PWM waveform 118 periods can result in adverse effects in circuits incorporating PWM control. For example, interruption in alternation of a PWM waveform 118 in a circuit using PWM to control power delivery to a primary side of a transformer (or other inductor) can result in overvoltage of a capacitor, or oversaturation of an inductor, potentially damaging a corresponding circuit.
FIG. 1C shows a prior art example of a count plot 130 of a PWM control counter 132 against time, and an example of a timing diagram 134 of a PWM waveform 136 generated using the control counter 132. The count plot 130 and the timing diagram 134 use the same time axis. The control counter 102 of FIG. 1A acts as a master control counter with respect to the control counter 132 of FIG. 1C. This means that the (slave) control counter 132 count (except during a period which spans or is next subsequent to a change in frequency or phase delay), values for the frequencies (maximum and minimum count values), and thresholds of FIG. 1C are the same as the (master) control counter 102 values for the frequencies and thresholds of FIG. 1A; except that the control counter 132 of FIG. 1C is phase shifted +90° with respect to the control counter 102 of FIG. 1A. This phase shift does not cause errors in the PWM waveform 136 because discontinuities 124 in the PWM waveform 136 do not occur at a rising edge threshold 138 or a falling edge threshold 140, and the thresholds 138, 140 are held constant. However, in typical embodiments, rising edge and/or falling edge thresholds are variable.